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rev. 0.21 12/07 copyright ? 2007 by silicon laboratories si8220 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si8220 2.5 a mp iso driver with o pto i nput features applications description the si8220 is a high-performance, pin-compatible upgrade for opto- coupled drivers, such as the hcpl-3 120. it utilizes silicon laboratories' proprietary silicon isolation te chnology, which provides 600 vdc (2.5 kvac rms ) withstand voltage per ul1577. this technology enables higher performance, reduced variatio n with temperature and age, tighter part-to-part matching, and superior common-mode rejection compared to opto-isolated drivers. while the input circuit mimics the characteristics of an led, less drive current is required, resulting in increased efficiency. propagation delay time is independent of input drive current, resulting in consistently short propagation time, tighter unit-to-unit variation, and greater input circuit design flexibility. ? upgrade for hcpl 3120, tlp250, and similar opto-drivers ? 50 ns propagation delay (independent of input drive current) ? 14x tighter part-to-part matching versus opto-drivers ? 600 vdc (2.5 kv rms ) output-to-input differential voltage ? 35 kv/s common-mode transient immunity ? under-voltage lockout protection with hysteresis ? resistant to temperature and aging effects ? gate driver supply voltage: 8 v to 24 v ? operating temperat ure range: ?40 to +125 oc ? cost-effective ? pb-free and rohs compliant ? igbt/ mosfet gate drives ? industrial control systems ? switch mode power supplies ? ups systems ? motor control drives si8220 nc nc anode cathode led emulator uv lockout vo vo vdd vss isolator rf transmitter rf receiver patent pending pin assignments: see page 16 1 2 3 4 8 7 6 5 nc anode cathode nc v ss v o v o v dd
si8220 2 rev. 0.21
si8220 rev. 0.21 3 t able of c ontents 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4. technical descript ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1. device behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2. device startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.3. under voltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5. applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1. power supply connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2. layout considerat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3. power dissipation considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5.4. input circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.5. parametric differences bet ween si8220 and hcpl-3120 opto dr iver . . . . . . . . . . . 14 6. regulatory information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 7. pin descriptions: si8220 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9. package outline: 8-pin pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
si8220 4 rev. 0.21 1. electrical specifications table 1. absolute maximum ratings* parameter conditions min typ max units storage temperature t stg ?65 ? +150 c ambient temperature under bias ?40 ? +125 c supply voltage ?0.6 ? 30 v input voltage ?0.5 ? v dd + 0.5 v lead solder temperature (10 s) if (avg) ??260 c maximum isolation voltage (v dd ? v ss )??3,000v dc *note: permanent device damage may occur if the absolute maximu m ratings are exceeded. functional operation should be restricted to the conditions specified in the operational sections of this data sheet. table 2. electrical characteristics v dd =12v, v ss = gnd, t a = ?40 to +125 c; typical specs at 25 c. parameter symbol test conditions min typ max units dc specifications power supply voltage v dd (v dd ? v ee )8?24v input current (on) i f(on) 5?10ma input voltage (off) v f(off) measured at anode with respect to cathode. ? 0.6 ? 1.6 v input forward voltage v f measured at anode with respect to cathode. i f =5ma. 1.7 ? 2.8 v output resistance high roh ? 2.7 ? output resistance low rol ? 1.0 ? output high current i oh i f = 0, figure a2 ? 1.5 ? a output low current i ol i f = 10 ma, figure a1 ? 2.5 ? a high-level outp ut voltage v oh i out = ?100 ma ? v dd ? 0.3 ? v low-level output voltage v ol v ss =gnd ? 0.1 ? v high level supply current output open i f =10ma ? 5 ? ma low level supply current output open v f = ?0.6 to +1.6 v ?5?ma input reverse breakdown voltage bv r i r =10a. measured at anode with respect to cathode. ?0.5 ? ?0.8 v input capacitance c in ?20?pf
si8220 rev. 0.21 5 undervoltage threshold ? v dd v dduv+ v dd rising 8 9 10 v undervoltage threshold hysteresis ? v dd v ddhys v dd falling ? 500 ? mv ac specifications propagation delay time to high output level t plh cl = 2000 pf ? ? 50 ns propagation delay time to low output level t phl cl = 2000 pf ? ? 50 ns uvlo turn-on delay t uvlo on ??50 ns uvlo turn-off delay t uvlo off ??50 output rise and fall time t r , t f cl = 200 pf ? ? 20 ns device start-up time t start time from v dd =v dd_uv+ to v o ?? 2 s table 2. electrical characteristics (continued) v dd =12v, v ss = gnd, t a = ?40 to +125 c; typical specs at 25 c. parameter symbol test conditions min typ max units
si8220 6 rev. 0.21 2. test circuits figure 1. iol test circuit figure 2. ioh test circuit 8 1 2 7 6 3 4 5 nc anode cathode nc v dd v o v o v ss 0.1 f + - v dd = 9.5 to 18 v i ol + - 2.5 v 8 1 2 7 5 6 3 4 nc anode cathode nc v dd v o v o v ss 0.1 f i f = 5 to 10 ma + - 4 v + - v dd = 9.5 to 18 v i oh
si8220 rev. 0.21 7 3. overview the si8220 is a pin-compatible upgrade for popular opto- isolated drivers, such as the hp/agilent/avago hcpl- 3120, toshiba tlp 250, and others. these products utilize silicon laboratories' proprietary silicon isolator technology, enabling fast propagation time while withstanding 600 vdc (2.5 kv rms ) from the input to output. the operation of this isolator is analogous to that of an opto-coupler, except that an rf carrier is modulated instead of light. this simple architecture provid es a robust isolated data path and requires no special considerations or initialization at start-up. as shown in figure 3, an isol ation channel consists of an rf transmitter and receiver separated by an rf transformer. figure 3. isolator operation input "a" turns the rf carrier on when high and off when low. the carrier is transmitted through the rf transformer to the output side demodulator, which consists of a receiver tuned to the carrier frequency. the demodulator asserts output "b" when sufficient in-band energy is detected. the driver output state follows that of output b. transmitter modulator rf oscillator demodulator receiver gate driver output b input a rf transformer
si8220 8 rev. 0.21 4. technical description 4.1. device behavior truth tables for the si8220 are summarized in table 3. 4.2. device startup output v o is held low during power-up until v dd rises above the uvlo threshold for a minimum time period of t start . following this, the output is high when the current flowing from anode to cathode is > i f(on) . device startup, normal operation, and shutdown behavior is shown in figure 4. figure 4. si8220 operating behavior ( i f > i f(min) when v f > v f(min) ) table 3. si8220 truth table summary cathode anode diode current (i f )v dd vo comments x x x < uvlo hi-z device turned off hi-z x 0 > uvlo l logic low state x hi-z 0 > uvlo l logic low state gnd gnd 0 > uvlo l logic low state vf vf 0 > uvlo l logic low state gnd1 vf < i f(on) > uvlo l logic low state gnd1 vf > i f(on) > uvlo h logic high state note: ?x? = don?t care. i f v o v dd t start t start v ddhys v dduv+ t phl t plh v f(on)
si8220 rev. 0.21 9 4.3. under voltage lockout (uvlo) the uvlo circuit unconditionally drives v o low when v dd is below the lockout threshold. referring to figure 5, upon power up, the si8220 is maintained in uvlo until v dd rises above v dduv+ . during power down, the si8220 enters uvlo when v dd falls below the uvlo threshold plus hysteresis (i.e., v dd < v dduv+ ? v ddhyst ). figure 5. si8220 uvlo response 6.5 10.5 v dduv+ (typ) output voltage (v o ) 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 supply voltage (v dd - v ss ) (v)
si8220 10 rev. 0.21 5. applications 5.1. power supply connections v ss can be biased at, above, or below ground as long as the voltage on v dd with respect to v ss is a maximum of 24 v. v dd decoupling capacitors should be placed as close to the package pins as possible. the optimum values for these capacitors depend on load current and the distance between the chip and its power source. a minimum 1 f capacitor is recommended. 5.2. layout considerations it is most important to minimize ringing in the drive path and noise on the v dd lines. care must be taken to minimize parasitic inductance in these paths by locating the si8220 as close to the device it is driving as possible. in addition, the v dd supply and ground trace paths must be kept short. for this reason, the use of power and ground planes is highly recommended. a split gr ound plane system having separate ground and v dd planes for power devices and small signal components provides the best overall noise performance. 5.3. power dissipation considerations proper system design must assure that the si8220 operates withi n safe thermal limits acro ss the entire load range. the si8220 total power dissipation is the sum of the power dissipated by bias supply current, internal switching losses, and power delivered to the load, as shown in equation 1. equation 1. the maximum allowable power dissipation for the si8220 is a function of the package thermal resistance, ambient temperature, and maximum allowable juncti on temperature, as shown in equation 2. equation 2. substituting values for p d(max) , t jmax , t a , and ja into equation 2 results in a maximum allowable total power dissipation of 0.95 w. the maximum allowable load is found by substituting this limit and the appropriate datasheet values from table 2 on page 4 into equation 1 an d simplifying. the result is equation 3, where v f =2.8v, i f = 10 ma, and v dd =18v. p d v f () i f () v dd () i qout () c int () v dd 2 () f () 2c l () v dd 2 () f () where: p d is the total si8220 device power dissipation (w) i f is the diode current (10 ma max) v f is the diode anode voltage (2.8 v max) i qout is the driver maximum bias curent (5 ma) c int is the internal parasitic capacitance (370 pf) v dd is the driver-side supply voltage (24 v max) f is the switching frequency (hz) ++ + = p dmax () t jmax t a ? ja --------------------------- where: p dmax () is the maximum allowable si8220 device power dissipation (w) t jmax is the si8220 maximum junction temperature (145 c) t a is the ambient temperature (c) ja is the si8220 package junction-to-air thermal resistance (125 c/w)
si8220 rev. 0.21 11 equation 3. a graph of equation 3 is shown in figure 6. each point along the load line in this graph represents the package dissipation-limited value of c l for the corresponding switching frequency. figure 6. maximum load vs. switching frequency c lmax () 1.35 10 3 ? f ----------------------------- - 1.85 ? 10 10 ? where: c lmax () is the maximum load (pf) allowable at switching frequency f = 100 1,000 10,000 0 500 1,000 1,500 2,000 2,500 frequency (khz) load (pf)
si8220 12 rev. 0.21 5.4. input circuit design opto driver manufacturers typically recommend the circ uits shown in figures 7 and 8. these circuits are specifically designed to improve op to-coupler input common-mode rejection and increase noise immunity. figure 7. opto driver input circuit figure 8. high cmr opto driver input circuit the optically-coupled driver circuit of figure 7 turns the led on when the control inpu t is high. however, internal capacitive coupling from the led to the power and ground conductors can momentarily force the led into its off state when the anode and cathode inputs are subjected to a high common-mode transient. the circuit shown in figure 8 addresses this issue by using a value of r1 suff iciently low to overdrive th e led, ensuring it remains on during an input common-mode transient. q1 shorts the led off in the low output state, again increasing common- mode transient immunity. some opto driver applicat ions also recommend reverse-biasing the led when the control input is off to prevent coupled noise from energizing the led. r1 1 2 3 4 opto driver +5v open drain or collector control input n/c anode cathode n/c 1 2 3 4 control input +5v r1 opto driver n/c anode cathode q1 n/c
si8220 rev. 0.21 13 the si8220 can be used with the input circuits shown in figures 7 and 8; however, so me applications will require increasing the value of r1 in order to limit i f to a maximum of 10 ma. the si8220 propagation delay and output drive do not change for values of i f between i f(min) and i f(max) . new designs should cons ider the input circuit configurations of figure 9, which are more efficient than those of figures 7 and 8. as shown, s1 represents any suitable switch, such as a bjt or mosfet, analog tran smission gate, processor i/o, etc. also, note that the si8220 input can be driven from the i/o port of any mcu or fpga capable of sourcing a minimum of 5 ma (see figure 9c). figure 9. si8220 other input circuit configurations 1 2 3 4 control input +5v r1 s1 si8220 n/c anode cathode n/c see text si8220 1 2 3 4 +5v r1 control input s1 n/c anode cathode n/c see text 1 2 3 4 r1 mcu i/o port pin si8220 n/c anode cathode n/c a b c
si8220 14 rev. 0.21 5.5. parametric di fferences between si8220 and hcpl-3120 opto driver the si8220 is designed to directly replace hcpl-3120 a nd similar opto drivers. parametric differences are summarized in table 4 below. 5.5.1. supply voltage and uvlo the supply voltage of the si8220 is limited to 24 v, and the uvlo voltage thresholds are scaled accordingly. this will not be an issue for opto repl acement applications operating with supply voltages of 24 v and below. 5.5.2. input diode differences the si8220 input circuit requires less current and has twic e the off-state noise margin compared to opto drivers. however, high cmr opto driver designs that overdrive the led (see figure 8) may require increasing the value of r1 to limit input current to 10 ma max. in addition, there is no benefit in driving the si8220 input diode into reverse bias when in the off state. consequently, opto driver circ uits using this technique shou ld either leave the negative bias circuitry unpopulated or modify the circuitry (e.g. add a clamp diode) to ensure that the anode pin of the si8220 is no more than -0.8 v with resp ect to the cathode when reverse-biased. table 4. parametric differences of si8220 vs. hcpl-3120 parameter si8220 hcpl-3120 units max supply voltage 24 30 v on state forward input current 5 to 10 7 to 16 ma off state input voltage ?0.6 to +1.6 ?0.3 to +0.8 v max reverse input voltage (i r = ?10 a) ?0.5 to ?0.8 ?5 v uvlo threshold (rising) 8.0 to 10.0 13.5 to 11.0 v uvlo threshold (falling) 9.3 to 7.3 12.0 to 9.7 v uvlo hysteresis 0.5 1.6 v rise/fall time into 10 in series with 10 nf tbd 100 ns
si8220 rev. 0.21 15 6. regulatory information table 5. regulatory information ul the si8220 is certified under the ul1577 component recognition program to provide basic insulation to 2500 v rms (1 minute). it is production tested at > 3000 v rms for 1 second. for more details, see file tbd. table 6. insulation and safety-related specifications parameter symbol test condition value unit minimum air gap (clearance) l(io1) 7.1 mm minimum external tracking (creepage) l(io2) 7.4 mm minimum internal gap (internal clearance) tbd mm resistance (input-output) 1 r io 10 12 capacitance (input-output) 1 c io f=1mhz tbd pf input capacitance 2 c i tbd pf notes: 1. to determine resistance and capacitance, the si8220 is co nverted into a 2-terminal device. pins 1?4 are shorted together to form the first terminal, and pins 5?8 are shor ted together to form the second terminal. the parameters are then measured between these two terminals. 2. measured from input pin to ground.
si8220 16 rev. 0.21 7. pin descriptions: si8220 figure 10. pin configuration table 7. pin descriptions pin name description 1 nc no connect. 2 anode anode of led emulator. v o follows the signal applied to this input with respect to the cathode input. 3 cathode cathode of led emulator. v o follows the signal applied to anod e with respect to this input. 4 nc no connect. 5v ss external mosfet source connection and ground reference for v dd . this terminal is typically connected to ground but may be tied to a negative or positive voltage. 6v o output signal. pins 6 and 7 are connected together internally. 7v o output signal. pins 6 and 7 are connected together internally. 8v dd output-side power supply input referenced to v ss (24 v max). 1 2 3 4 8 7 6 5 nc anode cathode nc v ss v o v o v dd
si8220 rev. 0.21 17 8. ordering guide part number package temp range SI8220-B-IP dip-8 ?40 to +125 c
si8220 18 rev. 0.21 9. package outline: 8-pin pdip figure 11. 8-pin pdip table 8. package dimensions dimension min nom max a??.210 a1 .015 ? ? b .014 .018 .022 b2 .045 .060 .070 b3 .030 .039 .045 c .008 .010 .014 d .355 .365 .400 e .300 .310 .325 e1 .240 .250 .280 e .100 bsc. eb ? ? .430 l .115 .130 .150 aaa ? ? .010 notes: 1. all dimensions shown are in inches unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-001, variation ba.
si8220 rev. 0.21 19 n otes :
si8220 20 rev. 0.21 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: powerproducts@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. the sale of this product contains no licens es to power-one?s intellectual property. contact power-one, inc. for appropriate lic enses.

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